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LTM4605
PIN FUNCTIONS
V IN (Bank 1): Power Input Pins. Apply input voltage be-
tween these pins and PGND pins. Recommend placing
input decoupling capacitance directly between V IN pins
and PGND pins.
V OUT (Bank 5): Power Output Pins. Apply output load
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins.
PGND (Bank 6): Power Ground Pins for Both Input and
Output Returns.
SW1, SW2 (Bank 4, Bank 2): Switch Nodes. The power
inductor is connected between SW1 and SW2.
R SENSE (Bank 3): Sensing Resistor Pin. The sensing resis-
tor is connected from this pin to PGND.
SENSE + (Pin A4): Positive Input to the Current Sense and
Reverse Current Detect Comparators.
SENSE – (Pin A5): Negative Input to the Current Sense and
Reverse Current Detect Comparators.
EXTV CC (Pin F6): External V CC Input. When EXTV CC exceeds
5.7V, an internal switch connects this pin to INTV CC and
shuts down the internal regulator so that the controller and
gate drive power is drawn from EXTV CC . Do not exceed
7V at this pin and ensure that EXTV CC < V IN .
INTV CC (Pin F5): Internal 6V Regulator Output. This pin is
for additional decoupling of the 6V internal regulator.
PLLIN (Pin B9): External Clock Synchronization Input
to the Phase Detector. This pin is internally terminated
to SGND with a 50k resistor. The phase-locked loop will
force the rising bottom gate signal of the controller to be
synchronized with the rising edge of PLLIN signal.
PLLFLTR (Pin B8): The lowpass ?lter of the phase-locked
loop is tied to this pin. This pin can also be used to set the
frequency of the internal oscillator with an AC or DC voltage.
See the Applications Information section for details.
STBYMD (Pin A10): LDO Control Pin. Determine whether
the internal LDO remains active when the controller is shut
down. See Operations section for details. If the STBYMD
pin is pulled to ground, the SS pin is internally pulled to
ground to disable start-up and thereby providing a single
control pin for turning off the controller. An internal de-
coupling capacitor is tied to this pin.
V FB (Pin B6): The Negative Input of the Error Ampli?er.
Internally, this pin is connected to V OUT with a 100k preci-
sion resistor. Different output voltages can be programmed
with an additional resistor between V FB and SGND pins.
See the Applications Information section.
FCB (Pin A9): Forced Continuous Control Input. The
voltage applied to this pin sets the operating mode of the
module. When the applied voltage is less than 0.8V, the
forced continuous current mode is active. When this pin
is allowed to ?oat, the Burst Mode operation is active in
boost operation and the skip cycle mode is active in buck
operation. When the pin is tied to INTV CC , the constant
frequency discontinuous current mode is active in buck or
boost operation. See the Applications Information section.
SGND (Pin A7): Signal Ground Pin. This pin connects to
PGND at output capacitor point.
COMP (Pin B7): Current Control Threshold and Error
Ampli?er Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V.
PGOOD (Pin B5): Output Voltage Power Good Indicator.
Open drain logic output that is pulled to ground when
the output voltage is not within ±7.5% of the regulation
point.
RUN (Pin A8): Run Control Pin. A voltage below 1.6V will
turn off the module. There is a 100k resistor between the
RUN pin and SGND in the module. Do not apply more than
6V to this pin. See Applications Information section.
SS (Pin A6): Soft-Start Pin. Soft-start reduces the input
power sources’ surge currents by gradually increasing the
controller’s current limit.
4605fc
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